1. Field of the Invention
Example embodiments of the present invention relate to a stacked semiconductor device and a method of manufacturing the stacked semiconductor device. More particularly, example embodiments of the present invention relate to a stacked semiconductor device, in which semiconductor structures such as transistors including a gate pattern and a source/drain region are vertically stacked, and a method of manufacturing the stacked semiconductor device having the vertically stacked semiconductor structures.
2. Description of the Related Art
As design rules of semiconductor devices have been recently decreased, sizes of semiconductor structures formed on substrates and distances between the semiconductor structures have been decreased. However, when the sizes and the distances of the semiconductor structures are continuously decreased on the same plane, resistances of the semiconductor structures may be increased, and thus electrical reliabilities of the semiconductor devices including the semiconductor structures may be degraded.
In order to solve the above problem, stacked semiconductor devices in which semiconductor structures are vertically stacked have been developed. Examples of the stacked semiconductor structures are disclosed in U.S. Pat. No. 6,538,330. The stacked semiconductor devices are mainly employed in a static random access memory (SRAM) device, a system-on-chip (SOC), etc.
The semiconductor structures in the stacked semiconductor device are formed in a plurality of insulation layers that are vertically stacked, and active layers that serve as channel regions are formed on the insulation layers. The active layers are mainly formed by a selective epitaxial growth (SEG) process using a semiconductor substrate, which may be partially exposed by a first opening formed through the insulation layer, as a seed layer. A plug is also formed in the first opening to fill up the first opening when the active layers are formed.
The vertically stacked insulation layers are patterned to form a second opening partially exposing the semiconductor substrate, and a conductive material is formed in the second opening so that the semiconductor structures in the stacked semiconductor device are electrically connected to one another. The second opening partially exposes not only an upper face of the semiconductor substrate but also side portions of the active layers, which are formed on the insulation layers.
However, as shown in FIG. 1, when the second opening is formed to expose the plug disposed on the semiconductor substrate but to leave the upper face of the semiconductor substrate intact, a resistance between the vertically stacked semiconductor structures may be increased because the plug does not include impurities so that the plug may have a relatively higher resistance compared to that of the semiconductor substrate having doped impurities.
Additionally, as shown in FIG. 2, the second opening may be formed to expose some portions of the semiconductor substrate in addition to the upper face of the semiconductor substrate because an etching degree of the insulation layers may be controlled only by a processing time when the second opening is formed. When the conductive material is formed in the second opening exposing the above portions of the semiconductor substrate, a leakage current may be generated in the semiconductor substrate.
In order to solve the above-mentioned problems, a stacked semiconductor device is disclosed in Korean Patent No. 10-0655664.
The stacked semiconductor device in the above Korean patent includes a first plug having impurities doped thereto and a second plug not having impurities. Thus, the etching degree of the insulation layers may be controlled by detecting the first plug having the impurities instead of measuring the processing time when the second opening is formed. The conductive material is formed in the second opening to be electrically connected to the first plug.
However, an additional process for doping impurities into the first plug is further performed in the above Korean patent so that time and cost of the process may be increased. Additionally, the semiconductor substrate may be damaged when an implantation process for doping the impurities into the first plug is performed. Furthermore, the first and second plugs have etching rates that are very similar to each other so that the etching degree of the insulation layers is not easily controlled by detecting the first plug.